1. Field of the Invention
The present invention relates to a method for fabrication of a semiconductor device having elements arranged with super-high density employing ion implantation for eliminating possible defects in the semiconductor device or inhibiting the occurrence or growth of such defects.
2. Description of the Prior Art
Recently, in the fabrication of semiconductor devices, it becomes common that elements are very densely arranged in a limited space so that the stress thereof is increased, which easily leads to growth of defects generated in the device. Such defects often generated in the conventional semiconductor devices are explained with reference to a metal-oxide-semiconductor (MOS) field effect transistor by way of example as shown in FIGS. 19(a) and 19(b).
In FIG. 19(a), a polysilicon film 130 to serve as a gate electrode and a side wall oxide film 142 for forming an LDD (lightly doped drain) structure are formed on a p-type monocrystal semiconductor substrate 105 via a silicon oxide layer 112 for the gate dielectric film. In the p-type monocrystal semiconductor substrate 105, there are formed semiconductor regions 161 which are to serve respectively as a source and a drain, by vertical ion implantation, specifically by vertically applying arsenic ion beams 300. At the same time, an amorphous region 171 involving some minute defects is formed on the semiconductor region 161 in the silicon substrate 105 to serve as an external base region due to some ion implantation damage. As shown in FIGS. 19(a) and 19(b), one particularly noticeable aspect of the conventional semiconductor device is that the amorphous region 171 formed by such generally vertical ion implantation has a configuration of its source/drain edge portion reversely tapered (acute-angled).
When the amorphous region 171 is subjected to heat treatment for recrystallization growth, as shown in FIG. 19(b), the crystallization growth is induced in the amorphous region 171 within the semiconductor substrate 105 in two directions nearly orthogonal to each other, one is perpendicular to the horizontal bottom boundary surface and the other is perpendicular to the vertical side boundary surface thereof, i.e., upward oriented direction 204 and sideways oriented direction 202. These two oriented crystallization growths finally collide with each other, resulting in that there occurs some local crystal discontinuity which causes a defect known as "void" 210 (a corner defect). When any stress is applied to this local defect, the void 210 leads to further growth of the defect. The occurrence of such local defect growth is reported by Tamura et al in "Nuclear Instruments and Methods", B37/38 (1989), p. 329.
In the conventional method of ion implantation as described above, the formation of such a void 210 naturally leads to frequent crystal defect occurrence in the corner, so that the crystal defect in the corner may extend to a PN junction of elements having high precision and further extend across the PN junction which is very sensitive to such a crystal defect. As a consequence, there occurs a trouble that various abnormal current (such as reverse leakage current and forward recombination current) flows through the defect. When there exists a defect at the PN junction or in the vicinity thereof, a forward or reverse abnormal current flows according to the polarity of the voltage applied to the PN junction. In such a case, no good performance characteristics can be expected with respect to the element. This adversely affects the yield of non-defective elements.
The existence of such defect poses a serious problem not only with respect to the source-to-drain junction in MOS, but also in the case of bipolar elements or the like, when an implantation of ions of high concentration is carried out using a mask to form an amorphous region. For example, when an amorphous region which has been formed by ion implantation having a high concentration of ions for forming an external base region of a vertical bipolar NPN transistor is recrystallized by heat treatment, some stressed defect is likely to occur in the external base region. The existence of such defect induces abnormal diffusion of an emitter-base junction formed in the vicinity of the defect. In order to avoid such an abnormal diffusion, it is desirable that the amorphous semiconductor region for the external base is to be converted into a normal monocrystal semiconductor region free from such a crystal defect to thereby inhibit such abnormal diffusion of the emitter.
Further, when such a crystal defect is formed, it is likely to cause a secondary deterioration to the crystalline structure of a junction. A variety of electrode wiring techniques have been developed such that after an external base or a source-drain region is formed, an opening for the base electrode or source/drain electrode is formed and then the semiconductor surface of the opening is silicidized (which is generally known as alloying of metal and semiconductor). In such technique, however, even though there may be not generated an electric leakage directly caused by a defective area involving a crystal defect, a nucleus of such defect, or the like which has been created in the external base or source-drain region as a result of recrystallization by a method of solid-phase epitaxial growth in the heat treatment, metal atoms of the silicide will cause abnormal diffusion of the defective area under the stress of silicidization, and this may easily result in destruction or deterioration (i.e., occurrence of electric leakage) of a base-emitter junction and/or source-drain junction adjacent to the defective area.
In view of the growing trend of super-high densification in the fabrication of semiconductor devices, therefore, the problem of mechanical stress due to heat treatment and otherwise will hereafter become more and more serious because increased mechanical stress causes a greater flow of leakage current, it being thus more and more difficult to fabricate non-defective semiconductor devices.